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| INTEGRATED CIRCUITS DATA SHEET TSA5059A 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer Product specification Supersedes data of 2000 Sep 19 File under Integrated Circuits, IC02 2000 Oct 24 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer FEATURES * Complete 2.7 GHz single chip system * Optimized for low phase noise * Selectable divide-by-two prescaler * Operation up to 2.3 GHz without divide-by-two prescaler (satellite zero-IF applications) and up to 2.7 GHz with divide-by-two prescaler * Selectable reference divider ratio * Selectable crystal or comparison frequency output * Four selectable charge pump currents * Four selectable I2C-bus addresses * Standard and fast mode I2C-bus * I2C-bus compatible with 3.3 and 5 V microcontrollers * 5-level Analog-to-Digital Converter (ADC) * Low power consumption * Three I/O ports and one output port. APPLICATIONS * Satellite zero-IF and non-zero-IF tuning systems * Digital set-top boxes. GENERAL DESCRIPTION The TSA5059A is a single chip PLL frequency synthesizer designed for satellite tuning systems up to 2.7 GHz. The RF preamplifier drives the 17-bit main divider enabling a step size equal to the comparison frequency, for an input frequency up to 2.3 GHz covering the complete satellite zero-IF frequency range. A fixed divide-by-two additional prescaler can be inserted between the preamplifier and the main divider for a frequency between 2.3 and 2.7 GHz. In this case, the step size is twice the comparison frequency. TSA5059A The comparison frequency is obtained from an on-chip crystal oscillator that can also be driven from an external source. Either the crystal frequency or the comparison frequency can be switched to the XT/COMP output pin to drive the reference input of another synthesizer or the clock input of a digital demodulation IC. Both divided and comparison frequency are compared into the fast phase detector which drives the charge pump. The loop amplifier is also on-chip, excepted an external NPN transistor to drive directly the 33 V tuning voltage. Control data is entered via the I2C-bus; five serial bytes are required to address the device, select the main divider ratio, the reference divider ratio, program the four output ports, set the charge pump current, select the prescaler by two, select the signal to switch to the XT/COMP output pin and select a specific test mode. Three of the four output ports can also be used as input ports and a 5-level ADC is provided. Digital information concerning the input ports and the ADC can be read out of the TSA5059A on the SDA line (one status byte) during a READ operation. A flag is set when the loop is `in-lock' and is read during a READ operation, as well as the Power-on reset flag. The device has four programmable addresses, programmed by applying a specific voltage at pin AS, enabling the use of multiple synthesizers in the same system. ORDERING INFORMATION TYPE NUMBER TSA5059AT TSA5059ATS PACKAGE NAME SO16 SSOP16 DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm VERSION SOT109-1 SOT369-1 2000 Oct 24 2 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer QUICK REFERENCE DATA VCC = 4.75 to 5.25 V; Tamb = -20 to +85 C; unless otherwise specified. SYMBOL VCC ICC fi(RF) Vi(RF)(rms) PARAMETER supply voltage supply current RF input frequency RF input voltage (RMS value) Tamb = 25 C note 1 fi(RF) from 900 to 2200 MHz; note 2 fi(RF) from 2.2 to 2.7 GHz; note 2 fxtal Tamb Tstg Notes 1. Bit PE needs to be set to logic 1 for a frequency higher than 2.3 GHz. 2. Asymmetrical drive on pin RFA or RFB; see Fig.3. crystal frequency ambient temperature storage temperature CONDITIONS MIN. 4.75 30 900 7.1 -30 22.4 -20 4 -20 -40 TYP. 5.0 37 - - - - - - - - TSA5059A MAX. 5.25 45 2700 300 +2.5 300 +2.5 16 +85 +150 V UNIT mA MHz mV dBm mV dBm MHz C C 2000 Oct 24 3 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer BLOCK DIAGRAM TSA5059A handbook, full pagewidth 3 XTAL 2 XTAL OSCILLATOR REFERENCE DIVIDER LOCK DETECT 4-BIT LATCH DIGITAL PHASE COMPARATOR RFA RFB 13 14 PRE AMP DIVIDER 1/2 17-BIT DIVIDER CHARGE PUMP 1-BIT LATCH 17-BIT LATCH DIVIDE RATIO 1 2-BIT LATCH AMP AS SCL SDA 4 6 5 I2C-BUS TRANSCEIVER 12 15 ADC 11 3-BIT ADC POWER-ON RESET 7 8 9 10 FCE711 XT/COMP CP 16 DRIVE VCC GND 3-BIT INPUT PORTS 4-BIT LATCH AND OUTPUT PORTS MODE CONTROL LOGIC TSA5059A P3 P2 P1 P0 Fig.1 Block diagram. 2000 Oct 24 4 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer PINNING SYMBOL CP XTAL XT/COMP AS SDA SCL P3 P2 P1 P0 ADC VCC RFA RFB GND DRIVE PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION charge pump output crystal oscillator input fxtal or fcomp signal output I2C-bus address selection input I2C-bus serial data input/output I2C-bus serial clock input general purpose output Port 3 general purpose input/output Port 2 general purpose input/output Port 1 general purpose input/output Port 0 analog-to-digital converter input supply voltage RF signal input A RF signal input B ground supply external NPN drive output P3 handbook, halfpage TSA5059A CP XTAL XT/COMP AS SDA 1 2 3 4 16 DRIVE 15 GND 14 RFB 13 RFA TSA5059A 5 12 VCC 11 ADC 10 P0 9 FCE713 SCL 6 7 P2 8 P1 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION The TSA5059A contains all the necessary elements but a reference source, a loop filter and an external NPN transistor to control a varicap tuned local oscillator forming a phase locked loop frequency synthesized source. The IC is designed in a high speed process with a fast phase detector to allow a high comparison frequency to reach a low phase noise level on the oscillator. The block diagram is shown in Fig.1. The RF signal is applied at pins RFA and RFB. Thanks to the input preamplifier a good sensitivity is provided. The output of the preamplifier is fed to the 17-bit programmable divider either through a divide-by-two prescaler or directly. Because of the internal high speed process, the RF divider is working for a frequency up to 2.3 GHz, without the need for the divide-by-two prescaler to be used. This prescaler is needed for frequencies above 2.3 GHz. The output of the 17-bit programmable divider fDIV is fed into the phase comparator, where it is compared in both phase and frequency with the comparison frequency fcomp. This frequency is derived from the signal present at pin XTAL, fxtal, divided down in the reference divider. It is possible either to connect a quartz crystal to pin XTAL and then using the on-chip crystal oscillator, or to feed this pin with a reference signal from an external source. The reference divider can have a dividing ratio selected from 16 different values between 2 and 320 (see Table 8). 2000 Oct 24 5 The output of the phase comparator drives the charge pump and the loop amplifier section. This amplifier requires the use of an external NPN transistor. Pin CP is the output of the charge pump, and pin DRIVE is the pin to connect the base of the external transistor. This transistor has its emitter grounded and the collector drives the tuning voltage to the varicap diode of the Voltage Controlled Oscillator (VCO). The loop filter has to be connected between pin CP and the collector of the external NPN transistor. In addition, it is possible to drive another PLL synthesizer, or the clock input of a digital demodulation IC, from pin XT/COMP. It is possible to select by software either fxtal, the crystal oscillator frequency or fcomp, the frequency present after the reference divider at this pin. It is also possible to switch off this output, in case it is not used. For test and alignment purposes, it is possible to release the drive output to be able to apply an external voltage on it, to select one of the three charge pump test modes, and to monitor half the fDIV at Port P0. See Table 10 for all possible modes. Four open-collector output ports are provided on the IC for general purpose; three of these can also be used as input ports. A 3-bit ADC is also available. The TSA5059A is controlled via the two-wire I2C-bus. For programming, there is one 7-bit module address and bit R/W for selecting READ or WRITE mode. Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer To be able to have more than one synthesizer in an I2C-bus system, one of four possible addresses is selected depending on the voltage applied at pin AS (see Table 3). The TSA5059A fulfils the fast mode I2C-bus, according to the Philips I2C-bus specification. The I2C-bus interface is designed in such a way that pins SCL and SDA can be connected either to 5 or 3.3 V pulled-up I2C-bus lines, allowing the PLL synthesizer to be connected directly to the bus lines of a 3.3 V microcontroller. WRITE mode: R/W = 0 After the address transmission (first byte), data bytes can be sent to the device (see Table 1). Four data bytes are needed to fully program the TSA5059A. The bus transceiver has an auto-increment facility that permits programming of the TSA5059A within one single transmission (address + 4 data bytes). The TSA5059A can also be partly programmed on the condition that the first data byte following the address is byte 2 or 4. The meaning of the bits in the data bytes is given in Table 1. The first bit of the first data byte transmitted indicates whether byte 2 (first bit is logic 0) or byte 4 (first bit is logic 1) will follow. Until an I2C-bus STOP condition is sent by the controller, additional data bytes can be entered without the need to re-address the device. Table 1 BYTE 1 2 3 4 5 Write data format DESCRIPTION address programmable divider programmable divider control data control data MSB 1 0 N7 1 C1 1 N14 N6 N16 C0 0 N13 N5 N15 XCE 0 N12 N4 PE XCS 0 N11 N3 R3 P3 MA1 N10 N2 R2 P2/T2 MA0 N9 N1 R1 P1/T1 LSB 0 N8 N0 R0 P0/T0 TSA5059A To allow a smooth frequency sweep for fine tuning, and while the data of the dividing ratio of the main divider is in data bytes 2, 3 and 4, it is necessary for changing the frequency to send the data bytes 2 to 5 in a repeated sending, or to finish an incomplete transmission by a STOP condition. Repeated sending of data bytes 2 and 3 without ending the transmission does not change the dividing ratio. To illustrate, the following data sequences will change the dividing ratio: * Bytes 2, 3, 4 and 5 * Bytes 4, 5, 2 and 3 * Bytes 2, 3, 4 and STOP * Bytes 4, 5, 2 and STOP * Bytes 2, 3 and STOP * Bytes 2 and STOP * Bytes 4 and STOP. CONTROL BIT A A A A A 2000 Oct 24 6 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer Table 2 Explanation of Table 1 DESCRIPTION programmable address bits; see Table 3 acknowledge bit TSA5059A BIT MA1 and MA0 A N16 to N0 PE R3 to R0 C1 and C0 XCE XCS T2, T1 and T0 P3, P2 and P1 P0 programmable main divider ratio control bits; N = N16 x 216 + N15 x 215 + ... + N1 x 21 + N0 prescaler enable (prescaler by 2 is active when bit PE = 1) programmable reference divider ratio control bits; see Table 8 charge pump current select bits; see Table 9 XT/COMP enable; XT/COMP output active when bit XCE = 1; see Table 10 XT/COMP select; signal select when bit XCE = 1; test mode enable when bit XCE = 0; see Table 10 test mode select when bit XCE = 0 and bit XCS = 1; see Table 10 Port P3, P2 and P1 output states Port P0 output state, except in test mode; see Table 10 Address selection The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having up to 4 synthesizers in one system. The relationship between MA1 and MA0 and the input voltage at pin AS is given in Table 3. Table 3 Address selection MA0 0 1 0 1 0 to 0.1VCC open-circuit 0.4VCC to 0.6VCC; note 1 0.9VCC to VCC VOLTAGE APPLIED TO PIN AS MA1 0 0 1 1 Note 1. This address is selected by connecting a 15 k resistor between pin AS and pin VCC. Status at Power-On Reset (POR) At power-on or when the supply voltage drops below approximately 2.75 V internal registers are set according to Table 4. Table 4 BYTE 1 2 3 4 5 Notes 1. X = don't care. 2. At Power-on reset, all output ports are in high-impedance state. 2000 Oct 24 7 Status at Power-on reset; note 1 DESCRIPTION address programmable divider programmable divider control data control data MSB 1 0 X 1 0 1 X X X 0 0 X X X 0 0 X X X 1 0 X X X X(2) MA1 X X X 1(2) MA0 X X X X(2) LSB 0 X X X X(2) CONTROL BIT A A A A A Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer READ mode: R/W = 1 Data can be read out of the TSA5059A by setting bit R/W to logic 1 (see Table 5). After the slave address has been recognized, the TSA5059A generates an acknowledge and the first data byte (status word) is transferred on the SDA line. Data is valid on the SDA line during a HIGH-level of the SCL clock signal. A second data byte can be read out of the TSA5059A if the controller generates an acknowledge on the SDA line. End of transmission will occur if no acknowledge from the controller occurs. The TSA5059A will then release the data line to allow the controller to generate a STOP condition. When ports P0 to P2 are used as inputs, they must be programmed in their high-impedance state. The POR flag is set to logic 1 when VCC drops below approximately 2.75 V and at power-on. Table 5 BYTE 1 2 Note 1. MSB is transmitted first. Table 6 Explanation of Table 5 BIT A MA1 and MA0 POR FL I2, I1 and I0 A2, A1 and A0 Table 7 A2 1 0 0 0 0 Note 1. Accuracy is 0.03VCC. ADC levels A1 0 1 1 0 0 A0 0 1 0 1 0 0.6VCC to VCC 0.45VCC to 0.6VCC 0.3VCC to 0.45VCC 0.15VCC to 0.3VCC 0 to 0.15VCC VOLTAGE APPLIED TO PIN ADC(1) acknowledge bit programmable address bits; see Table 3 Power-on reset flag (bit POR = 1 at power-on) in-lock flag (bit FL = 1 when the loop is phase-locked) digital information for I/O ports P2, P1 and P0 respectively digital outputs of the 5-level ADC; see Table 7 DESCRIPTION Read data format DESCRIPTION address status byte MSB(1) 1 POR 1 FL 0 I2 0 I1 0 I0 MA1 A2 MA0 A1 LSB 1 A0 TSA5059A It is reset to logic 0 when an end of data is detected by the TSA5059A (end of a READ sequence). Control of the loop is made possible with the in-lock flag which indicates when the loop is phase-locked (bit FL = 1). The bits I2, I1 and I0 represent the status of the I/O ports P2, P1 and P0 respectively. A logic 0 indicates a LOW-level and a logic 1 indicates a HIGH-level. A built-in 5-level ADC is available at pin ADC. This converter can be used to feed AFC information to the microcontroller through the I2C-bus. The relationship between bits A2, A1, A0 and the input voltage at pin ADC is given in Table 7. CONTROL BIT A - 2000 Oct 24 8 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer Reference divider ratio The reference divider ratio is set by 4 bits in the WRITE mode, giving 16 different ratios which allow to adjust the comparison frequency to different values, depending on the compromise which has to be found between step size and phase noise. Table 8 R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1. Only valid when the IC is used with a 4 MHz crystal. Charge pump current 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Reference dividing ratios R2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R0 RATIO 2 4 8 16 32 64 128 256 24 5 10 20 40 80 160 320 COMPARISON FREQUENCY(1) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 15.625 kHz 166.67 kHz 800 kHz 400 kHz 200 kHz 100 kHz 50 kHz 25 kHz 12.5 kHz STEP BIT PE = 0(1) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 15.625 kHz 166.67 kHz 800 kHz 400 kHz 200 kHz 100 kHz 50 kHz 25 kHz 12.5 kHz TSA5059A Table 8 shows the different dividing ratios and the corresponding comparison frequencies and step size, assuming the device is provided with a 4 MHz signal at pin XTAL. BIT PE = 1(1) 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 333.33 kHz 1.6 MHz 800 kHz 400 kHz 200 kHz 100 kHz 50 kHz 25 kHz The charge pump current can be chosen from 4 different values depending on the value of bits C1 and C0 in the I2C-bus byte 4 according to Table 9. Table 9 Charge pump current C1 0 0 1 1 C0 MIN. 0 1 0 1 100 210 450 920 Icp (A) (absolute value) TYP. 135 280 600 1230 MAX. 170 350 750 1540 2000 Oct 24 9 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer XT/COMP frequency output It is possible to output either the crystal or the comparison frequency at pin XT/COMP to be used in the application. For example, to drive a second PLL synthesizer saving a quartz crystal. To output fxtal it is necessary to set bit XCE to logic 1 and bit XCS to logic 0 or bit XCE to logic 0 and bit XCS to logic 1 during a test mode, while to output fcomp it is necessary to set both bits XCE and XCS to logic 1. If the output signal at this pin is not used it is recommended to disable it by setting both bits XCE and XCS to logic 0. Table 10 shows how this pin is programmed. At power-on the XT/COMP output is set with the fxtal signal selected. Prescaler enable The TSA5059A is able to work with the relation fcomp = step size for an input frequency up to 2.3 GHz, covering the complete satellite zero-IF frequency range. Table 10 XT/COMP and test mode selection; note 1 XCE 0 1 1 0 0 0 0 0 XCS 0 0 1 1 1 1 1 1 T2 X X X 0 0 0 0 1 T1 X X X 0 0 1 1 X T0 X X X 0 1 0 1 X XT/COMP OUTPUT disabled fxtal fcomp fxtal fxtal fxtal fxtal fxtal TSA5059A For applications with an input frequency higher than 2.3 GHz it is necessary to use the prescaler by 2. The prescaler is selected by setting bit PE to logic 1 and it is not in use if bit PE is set to logic 0. For satellite zero-IF applications (frequency between 950 and 2150 MHz), and especially if it is important to reach a low phase noise on the controlled VCO, it is recommended to set bit PE to logic 0 and not to use the prescaler allowing the comparison frequency to be equal to the step size. Test modes It is possible to access the test modes by setting bit XCE to logic 0 and bit XCS to logic 1. One specific test mode is then selected using bits T2, T1 and T0 as described in Table 10. TEST MODE normal operation normal operation normal operation test operation: charge pump sink; status byte bit FL = 1 test operation: charge pump source; status byte bit FL = 0 test operation: charge pump disabled; status byte bit FL = 0 test operation: 12fDIV switched to Port P0 test operation: drive output (pin DRIVE) is off (low-voltage) to allow the tuning voltage to reach the maximum value; note 2 Notes 1. X = don't care. 2. Status at Power-on reset. 2000 Oct 24 10 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1. SYMBOL VCC Vn supply voltage voltage on pins CP, XTAL, XT/COMP, AS, P0, P1, P2, P3, ADC, RFA and RFB SCL and SDA IO(drive) IO(SDA) IO(Px) IO(Px) Tamb Tstg Tj(max) Note output current on pin DRIVE serial data output current P0, P1, P2 and P3 output current sum of currents in P0, P1, P2 and P3 ambient temperature storage temperature maximum junction temperature port switched on -0.3 -0.3 -1 -1.0 -1.0 - -20 -40 - PARAMETER CONDITIONS MIN. -0.3 TSA5059A MAX. +6.0 V UNIT VCC + 0.3 V +6.0 +1 +10.0 +20.0 50.0 +85 +150 150 V mA mA mA mA C C C 1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage. Maximum ratings cannot be accumulated. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER TSA5059AT TSA5059ATS CONDITIONS VALUE 115 144 UNIT K/W K/W thermal resistance from junction to ambient in free air 2000 Oct 24 11 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer TSA5059A CHARACTERISTICS VCC = 4.75 to 5.25 V; Tamb = -20 to +85 C; fxtal = 4 MHz; measured according to Fig.4; unless otherwise specified. SYMBOL Supply (pin VCC) VCC ICC VCC(POR) fi(RF) Vi(RF)(rms) supply voltage supply current Tamb = 25 C supply voltage below which POR is active Tamb = 25 C RF input frequency RF input voltage (RMS value) fi(RF) between 900 and 2200 MHz; note 1 4.75 30 - 900 7.1 -30 5.0 37 2.75 - - - - - - - - - - 680 - 40 - - 5.25 45 - 2700 300 +2.5 300 +2.5 - - 131071 262142 V mA V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RF inputs (pins RFA and RFB) MHz mV dBm mV dBm pF fi(RF) between 2.2 and 22.4 2.7 GHz; notes 1 and 2 -20 Zi(RF) Ci(RF) MDR RF input impedance RF input capacitance main divider ratio see Fig.6 see Fig.6 prescaler disabled prescaler enabled Crystal oscillator (pin XTAL) fxtal ZXTAL ZXTAL PXTAL fi(ext) Vi(ext)(p-p) crystal frequency crystal oscillator negative impedance recommended crystal series resistance crystal drive level external reference input frequency external reference input voltage (peak-to-peak value) 4 MHz crystal 4 MHz crystal 4 MHz crystal; note 3 note 4 note 4 4 400 - - 2 200 - - 64 128 16 - 200 - 20 500 MHz W MHz mV Phase comparator and charge pump fcomp Ncomp comparison frequency equivalent phase noise at the phase detector input charge pump current fcomp = 250 kHz; C1 = C0 = 1; in the loop bandwidth C1 = 0; C0 = 0 C1 = 0; C0 = 1 C1 = 1; C0 = 0 C1 = 1; C0 = 1 ILO(cp) VO(drive) IO(drive) charge pump output leakage current DRIVE output (pin DRIVE) output voltage when the charge pump is sinking current output current when the charge pump is sourcing current XCE = 0; XCS = 1; T2 = 0; T1 = 0; T0 = 0 XCE = 0; XCS = 1; T2 = 0; T1 = 0; T0 = 1 - 100 140 250 250 - mV A - - - -157 2 - MHz dBc/Hz Icp 100 210 450 920 -10 135 280 600 1230 0 170 350 750 1540 +10 A A A A nA 2000 Oct 24 12 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer SYMBOL PARAMETER CONDITIONS - - - - 3.0 - -10 - -0.5 - 2.3 VIH = 5.5 V VCC = 5.5 V VCC = 0 V ILIL fSCL VO(ack) Notes 1. Asymmetrical drive on pin RFA or RFB; see Fig.3. 2. Bit PE needs to be set to logic 1 for a frequency higher than 2.3 GHz. LOW-level input leakage current SCL clock frequency VIL = 0 V; VCC = 5.5 V - - -10 - Isink = 3 mA - - - - - - MIN. TYP. TSA5059A MAX. - 10 0.4 1.5 - 10 - 1 - 1.5 - 10 10 - 400 UNIT XT/COMP output (pin XT/COMP) Vo(p-p) IlO VO(sat) VIL VIH ILIH ILIL ILIH ILIL VIL VIH ILIH AC output voltage (peak-to-peak value) XCE = 1 400 - 0.2 - - - - - - - - mV A V V V A A mA mA Input/output and output ports (pins P0, P1, P2 and P3) port leakage current output port saturation voltage LOW-level input voltage HIGH-level input voltage port off; VO = VCC port on; Isink = 10 mA ADC input (pin ADC) HIGH-level input leakage current LOW-level input leakage current VADC = VCC VADC = 0 V VAS = VCC VAS = 0 V Address selection (pin AS) HIGH-level input leakage current LOW-level input leakage current SCL and SDA inputs (pins SCL and SDA) LOW-level input voltage HIGH-level input voltage HIGH-level input leakage current V V A A A kHz SDA output (pin SDA) output voltage during acknowledge 0.4 V 3. The drive level is expected with the crystal at series resonance with a series resistance of 50 . The value will be different with another crystal. 4. To drive pin XTAL from the pin XT/COMP of another TSA5059A, couple the signal using a capacitor of 1 nF (to remove the DC level) in series with an 1.2 k resistor (see Fig.5). 2000 Oct 24 13 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer TSA5059A handbook, full pagewidth +6 Vi(RF) (dBm) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 500 1000 1500 2000 2500 Guaranteed area FCE416 3000 f (MHz) Fig.3 Sensitivity curve. 2000 Oct 24 14 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer APPLICATION INFORMATION TSA5059A An example of a typical application is given in Fig.4. In this application the VCO centre frequency is 1.5 GHz with a slope of 100 MHz/V. The expected loop bandwidth is 10 kHz with a charge pump current of 555 A and fcomp of 250 kHz. Filter components need to be adapted to each application depending on the VCO characteristics and the required performance of the loop. handbook, full pagewidth 33 V 5V 27 k 2.7 k 3.9 k 47 nF 2.2 nF 1 nF tuning voltage CP 4 MHz 18 pF XTAL 1 2 3 4 5 6 7 8 16 15 14 13 DRIVE GND RFB RFA VCC ADC P0 P1 BC847 VCO output VCO XT/COMP AS SDA SCL P3 MICROCONTROLLER P2 1 nF 1 nF 10 nF FCE714 TSA5059A 12 11 10 9 Fig.4 Typical application. Loop bandwidth Most of the applications the TSA5059A are dedicated for require a large loop bandwidth, in the order of a few kHz to a few tens of kHz. The calculation of the loop filter elements has to be done for each application, while it depends on the VCO slope and phase noise as well as the reference frequency and charge pump current. A simulation of the loop can easily be done by using the SIMPATA software from Philips. Reference source The TSA5059A is well suited to be used with a 4 MHz crystal connected to pin XTAL. Philips crystal ordering code 4322 143 04093 is recommended in this case. It is however possible to use a crystal with an higher frequency (up to 16 MHz) to improve the noise performance. When choosing a crystal, one should take notice to select a crystal able to withstand the drive level of the TSA5059A without suffering from accelerated ageing. It is also possible to feed pin XTAL with an external signal between 2 and 20 MHz, coming from an external oscillator or from the pin XT/COMP of another TSA5059A, when more than one synthesizer is present in the same application. Then the application given in Fig.5 should be used. If the signal at pin XT/COMP is not used in an application the output should be switched off (XCE = 0 and XCS = 0). This pin should then be left open. 2000 Oct 24 15 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer TSA5059A handbook, full pagewidth 4 MHz 18 pF 1 2 3 4 5 6 7 8 16 1.0 nF 15 1.2 k 14 13 1 2 3 4 5 6 7 8 16 15 14 13 TSA5059A 12 11 10 9 TSA5059A 12 11 10 9 FCE715 Fig.5 Application for using one crystal with two TSA5059As. The best way to avoid any I2C-bus crosstalk in the application (i.e. parasitic coupling between the I2C-bus lines and the VCO coil) is to avoid the I2C-bus signal to come in the RF part by using an I2C-bus gate that allows only the messages for the PLL to go to the PLL and to avoid unnecessary repeated sending. Such a gate is integrated in most of the Philips digital demodulators. I2C-bus crosstalk The TSA5059A includes a loop amplifier that requires an external NPN transistor. Care should be taken in the layout of the application to ground the emitter of the NPN transistor as close as possible to the ground of the VCO. 2000 Oct 24 16 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer RF input impedance TSA5059A handbook, full pagewidth 1 0.5 2 0.2 5 10 +j 0 -j 2.7GHz 0.2 5 0.2 0.5 1 2 5 10 900 MHz 10 0.5 1 2 FCE418 Fig.6 RF input impedance. 2000 Oct 24 17 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm TSA5059A SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 0.010 0.057 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 8 0o o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 2000 Oct 24 18 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm TSA5059A SOT369-1 D E A X c y HE vM A Z 16 9 Q A2 pin 1 index A1 (A 3) Lp L A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 2000 Oct 24 19 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering TSA5059A If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2000 Oct 24 20 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer Suitability of surface mount IC packages for wave and reflow soldering methods TSA5059A SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2000 Oct 24 21 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1) TSA5059A This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Preliminary specification Qualification Product specification Production Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Oct 24 22 Philips Semiconductors Product specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer NOTES TSA5059A 2000 Oct 24 23 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 70 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/04/pp24 Date of release: 2000 Oct 24 Document order number: 9397 750 07653 |
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